1. Anastassia Ailamaki , David J. DeWitt , Mark D. Hill , and Marios Skounakis . 2001 . Weaving relations for cache performance . VLDB 2001 - Proc. 27th Int. Conf. Very Large Data Bases (2001), 169–180. Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, and Marios Skounakis. 2001. Weaving relations for cache performance. VLDB 2001 - Proc. 27th Int. Conf. Very Large Data Bases (2001), 169–180.
2. Cisco Corp. [n. d.]. Cisco Global Cloud Index: Forecast and Methodology , 2016 -21. Cisco Corp.[n. d.]. Cisco Global Cloud Index: Forecast and Methodology, 2016-21.
3. Fabrice Devaux . 2019. The true Processing In Memory accelerator . In IEEE Hot Chips . Fabrice Devaux. 2019. The true Processing In Memory accelerator. In IEEE Hot Chips.
4. The architecture of the DIVA processing-in-memory chip
5. Duncan Elliott 1999. Computational RAM: Implementing Processors in Memory . IEEE Des. Test 1999 (1999). Duncan Elliott 1999. Computational RAM: Implementing Processors in Memory. IEEE Des. Test 1999 (1999).