Finding and Finessing Static Islands in Dynamically Scheduled Circuits

Author:

Cheng Jianyi1,Wickerson John1,Constantinides George A.1

Affiliation:

1. Imperial College London, London, United Kingdom

Funder

Engineering and Physical Sciences Research Council

Publisher

ACM

Reference51 articles.

1. Integrated scheduling, allocation and module selection for design-space exploration in high-level synthesis

2. Runtime dependency analysis for loop pipelining in high-level synthesis

3. Mihai Budiu and Seth Copen Goldstein . 2002 . Pegasus: An Efficient Intermediate Representation . Technical Report Carnegie Mellon University-CS-02--107. Carnegie Mellon University . 20 pages. Mihai Budiu and Seth Copen Goldstein. 2002. Pegasus: An Efficient Intermediate Representation . Technical Report Carnegie Mellon University-CS-02--107. Carnegie Mellon University. 20 pages.

4. Modulo SDC scheduling with recurrence minimization in high-level synthesis

5. Andrew Canis , Jongsok Choi , Mark Aldham , Victor Zhang , Ahmed Kammoona , Tomasz Czajkowski , Stephen D. Brown , and Jason H . Anderson . 2013 . LegUp: An Open-source High-level Synthesis Tool for FPGA-based Processor/Accelerator Systems . ACM Trans. Embed. Comput. Syst. , Vol. 13 , 2, Article 24 (Sept. 2013), bibinfonumpages 27 pages. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz Czajkowski, Stephen D. Brown, and Jason H. Anderson. 2013. LegUp: An Open-source High-level Synthesis Tool for FPGA-based Processor/Accelerator Systems . ACM Trans. Embed. Comput. Syst. , Vol. 13, 2, Article 24 (Sept. 2013), bibinfonumpages27 pages.

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1. A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12

2. Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets;IEEE Transactions on Computers;2023-11-01

3. Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis;2023 33rd International Conference on Field-Programmable Logic and Applications (FPL);2023-09-04

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