Efficient and Effective Neural Networks for Automatic Test Pattern Generation
Author:
Affiliation:
1. University of Wisconsin-Madison, Madison, Wisconsin, USA
2. University of Wisconsin-Madison, Madison, USA
Funder
National Science Foundation
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3670474.3685939
Reference18 articles.
1. F. Brglez. 1984. On Testability Analysis of Combinational Circuits. IEEE International Symposium on Circuits and Systems (1984), 221--225.
2. On the Acceleration of Test Generation Algorithms;Shimono Fujiwara;IEEE Trans. Comput. C-32,1983
3. H. K. Lee and D. S. Ha. 1993. On the Generation of Test Patterns for Combinational Circuits. Technical Report No. 12--93. Department of Electrical Engineering Virginia Polytechnic Institute and State University.
4. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
5. J. Patel and S. Patel. 1985. What Heuristics are Best for PODEM? First International Workshop on VLSI Design (1985), 1--20.
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