Affiliation:
1. Florida State University, Tallahassee, FL
2. Oracle Corporation, Redwood City, CA
3. University of Virginia, Charlottesville, VA
4. University of Illinois at Urbana-Champaign, Urbana, IL
Abstract
Software designers face many challenges when developing applications for embedded systems. A major challenge is meeting the conflicting constraints of speed, code density, and power consumption. Traditional optimizing compiler technology is usually of little help in addressing this challenge. To meet speed, power, and size constraints, application developers typically resort to hand-coded assembly language. The results are software systems that are not portable, less robust, and more costly to develop and maintain. This paper describes a new code improvement paradigm implemented in a system called
vista
that can help achieve the cost/performance trade-offs that embedded applications demand. Unlike traditional compilation systems where the smallest unit of compilation is typically a function and the programmer has no control over the code improvement process other than what types of code improvements to perform, the
vista
system opens the code improvement process and gives the application programmer, when necessary, the ability to finely control it. In particular,
vista
allows the application developer to (1) direct the order and scope in which the code improvement phases are applied, (2) manually specify code transformations, (3) undo previously applied transformations, and (4) view the low-level program representation graphically. vista can be used by embedded systems developers to produce applications, by compiler writers to prototype and debug new low-level code transformations, and by instructors to illustrate code transformations (e.g., in a compilers course).
Publisher
Association for Computing Machinery (ACM)
Subject
Computer Graphics and Computer-Aided Design,Software
Reference26 articles.
1. Design and implementation of the UW Illustrated compiler
2. Start/Pat: a parallel-programming toolkit
3. M. E. Benitez. Retargetable Register Allocation. PhD thesis University of Virginia 1994]] M. E. Benitez. Retargetable Register Allocation. PhD thesis University of Virginia 1994]]
4. A portable global optimizer and linker
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