A Precise Measurement Platform for LPDDR4 Memories
Author:
Affiliation:
1. Microelectronics Systems Design Research Group, University of Kaiserslautern-Landau, Germany
2. Fraunhofer IESE, Germany
3. Fraunhofer IESE, Germany and University of Würzburg, Germany
Funder
BMBF
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3631882.3631899
Reference15 articles.
1. An FPGA-based test platform for analyzing data retention time distribution of DRAMs
2. A Platform to Analyze DDR3 DRAM’s Power and Retention Time
3. Matthias Jung, Deepak M. Mathew, Christian Weis, and Norbert Wehn. 2016. Efficient Reliability Management in SoCs - An Approximate DRAM Perspective. In 21st Asia and South Pacific Design Automation Conference (ASP-DAC).
4. A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs
5. 23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices
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