Lightweight Emulation of Virtual Channels using Swaps

Author:

Parasar Mayank1,Krishna Tushar1

Affiliation:

1. Georgia Institute of Technology, Atlanta, Georgia

Publisher

ACM

Reference14 articles.

1. The gem5 simulator

2. N. Chrysostomos etal 2006. ViChaR: A dynamic virtual channel regulator for network-on-chip routers. In MICRO' 06. IEEE 333--346. N. Chrysostomos et al. 2006. ViChaR: A dynamic virtual channel regulator for network-on-chip routers. In MICRO' 06. IEEE 333--346.

3. C. Clauss etal 2011. Evaluation and improvements of programming models for the Intel SCC many-core processor. In HPCS. 10.1109/HPCSim.2011.5999870 C. Clauss et al. 2011. Evaluation and improvements of programming models for the Intel SCC many-core processor. In HPCS. 10.1109/HPCSim.2011.5999870

4. B. Daya etal 2014. SCORPIO: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. In ISCA. B. Daya et al. 2014. SCORPIO: a 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. In ISCA.

5. Natalie Enright Jerger Tushar Krishna and Li-Shiuan Peh. 2017. On-chip Networks. Morgan & Claypool Publishers. Natalie Enright Jerger Tushar Krishna and Li-Shiuan Peh. 2017. On-chip Networks. Morgan & Claypool Publishers.

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1. Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-05

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