An Efficient Method of DRC Violation Prediction with a Serial Deep Learning Model

Abstract

In VLSI design, the utilization of Design Rule Check (DRC) tools in the early stage is crucial for predicting and resolving violations, thereby expediting the physical design process. In our study, we present an efficient model that predicts DRC violations prior to the routing stage. Additionally, our model incorporates a sliding window technique to enhance the feature extraction process. We extract structural features using GCN networks and utilize feature reuse techniques to fully recover the lost information in neural layers, which serves as input to the CNN model, resulting in more accurate hotspot prediction. The experimental results demonstrate that our model successfully identifies 95.78% of DRC violations, with a mere 4.17% false alarm rate. Not only does our method deliver improved feature preprocessing results, but it also enhances prediction accuracy compared to alternative approaches.