Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs

Author:

Lin Jai-Ming1,Hsieh Hao-Yuan1,Kung Hsuan1,Lin Hao-Jia1

Affiliation:

1. National Cheng Kung University, Tainan, Taiwan

Publisher

ACM

Reference28 articles.

1. P. Batude CMOS sequential integration." in Proc . IEEE IEDM , pp. 1 -- 4 , Dec 2009 . P. Batude et al., "Advances in 3D CMOS sequential integration." in Proc. IEEE IEDM, pp. 1--4, Dec 2009.

2. P. Batude , " Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length," 2011 Symposium on VLSI Technology - Digest of Technical Papers , pp. 158 -- 159 , 2011 . P. Batude et al., "Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length," 2011 Symposium on VLSI Technology - Digest of Technical Papers, pp. 158--159, 2011.

3. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

4. RePlAce: advancing solution quality and routability validation in global placement;Cheng C.;IEEE TCAD,2019

5. J. Cong and G. Luo , " A multilevel analytical placement for 3D ICs," in Proc . ASP-DAC , pp. 361 -- 366 , Feb. 2009 . J. Cong and G. Luo, "A multilevel analytical placement for 3D ICs," in Proc. ASP-DAC, pp. 361--366, Feb. 2009.

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1. HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

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