An Efficient Approximate Node Merging with an Error Rate Guarantee
Author:
Affiliation:
1. Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
2. Department of Computer Science and Engineering, Yuan Ze University, Taoyuan, Taiwan, R.O.C.
Funder
Ministry of Science and Technology, Taiwan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3394885.3431550
Reference28 articles.
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Efficient Approach to Iterative Network Pruning;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
2. Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis;2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2023-06-20
3. Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16
4. A Catalog-Based AIG-Rewriting Approach to the Design of Approximate Components;IEEE Transactions on Emerging Topics in Computing;2023-01-01
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