Model Checking and Synthesis for Strategic Timed CTL using Strategies in Rewriting Logic-Reference-Cited by-同舟云学术

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Model Checking and Synthesis for Strategic Timed CTL using Strategies in Rewriting Logic

Published:2024-09-09 Issue: Volume: Page:1-14
ISSN:
Container-title:Proceedings of the 26th International Symposium on Principles and Practice of Declarative Programming
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Author:

Arias Jaime¹^ORCID,Olarte Carlos¹^ORCID,Penczek Wojciech²^ORCID,Petrucci Laure¹^ORCID,Sidoruk Teofil²^ORCID

Affiliation:

1. Université Sorbonne Paris Nord, LIPN, CNRS UMR 7030, France

2. Warsaw University of Technology, Poland

Funder

PHC Polonium

PHC Aurora

NCBR Poland and FNR Luxembourg

Minciencias

NATO Science for Peace and Security Programme

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3678232.3678240

Reference63 articles.

1. Model-Checking in Dense Real-Time

2. Rajeev Alur and David L. Dill. 1990. Automata For Modeling Real-Time Systems. In ICALP(LNCS, Vol. 443). Springer, 322–335.

3. Real-Time Logics: Complexity and Expressiveness

4. Rajeev Alur, Thomas A. Henzinger, and Orna Kupferman. 1997. Alternating-time Temporal Logic. In FOCS. IEEE Computer Society, 100–109.

5. Alternating-time temporal logic

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