HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment-Reference-Cited by-同舟云学术

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment

Published:2021-05-24 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2021 ACM Asia Conference on Computer and Communications Security
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Author:

Nasahl Pascal¹,Schilling Robert¹,Werner Mario¹,Mangard Stefan²

Affiliation:

1. Graz University of Technology, Graz, Austria

2. Graz University of Technology & Lamarr Security Research, Graz, Austria

Funder

European Research Council

Austrian Federal Ministry of Economy, Family and Youth

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3433210.3453112

Reference65 articles.

1. 2018. CVE-2016-10423. 2018. CVE-2016-10423.

2. Control-flow integrity principles, implementations, and applications

3. Denis Andzakovic. 2019. https://pulsesecurity.co.nz/articles/TPM-sniffing Extracting Bitlocker Keys from a TPM. Denis Andzakovic. 2019. https://pulsesecurity.co.nz/articles/TPM-sniffing Extracting Bitlocker Keys from a TPM.

4. Apple. 2020. https://support.apple.com/en-us/HT208862 About the Apple T2 Security Chip. Apple. 2020. https://support.apple.com/en-us/HT208862 About the Apple T2 Security Chip.

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