Nanopipelined threshold network synthesis

Abstract

Threshold logic gates allow for complex multiinput functions to be implemented using a single gate thereby reducing the power and area of a circuit. Clocked threshold gates are nanopipelined to increase network throughput. It is shown that synthesis methods that do not consider the synchronization of the nanopipeline can produce an enormous amount of buffers. The proposed algorithm synthesizes a Boolean network into a nanopipelined threshold logic network by minimizing not only the number of combinational clusters but also the associated buffer insertion overhead.