Affiliation:
1. Xilinx Inc.
2. University of California, Berkeley
Abstract
This article presents a new technology mapper, WireMap. The mapper uses an
edge flow
heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). On academic benchmark (ISCAS, MCNC, and ITC designs), the average edge reduction of 9.3% is achieved while maintaining depth and LUT count compared to state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wirelength, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. This technique is applied in the Xilinx ISE Design tool to evaluate its effect on industrial Virtex5 circuits. In a set of 20 large designs, we find the edge reduction is 6.8% while total wirelength measured in the placer is reduced by 3.6%. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5- and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual-output LUT structure found in commercial FPGAs. For academic benchmarks, WireMap leads to 9.4% fewer dual-output LUTs after merging. For the industrial designs, WireMap leads to 6.3% fewer dual-output Virtex5 LUTs.
Publisher
Association for Computing Machinery (ACM)
Reference21 articles.
1. Architecture-specific packing for virtex-5 FPGAs
2. Altera. 2008. Stratix III device handbook. http://www.altera.com/literature/hb/stx3/stratix3_handbook.pdf. Altera. 2008. Stratix III device handbook. http://www.altera.com/literature/hb/stx3/stratix3_handbook.pdf.
3. Altera. 2004. Improving FPGA performance and area using an adaptive logic module. http://www.altera.com/literature/cp/cp-01004.pdf. Altera. 2004. Improving FPGA performance and area using an adaptive logic module. http://www.altera.com/literature/cp/cp-01004.pdf.
4. Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic. Betz V. Rose J. and Marquardt A. 1999. Architecture and CAD for Deep-Submicron FPGAs . Kluwer Academic.
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