The impact of cache inclusion policies on cache management techniques

Author:

Backes Luna1,Jiménez Daniel A.2

Affiliation:

1. Texas A&M University

2. Texas A&M University and Barcelona Supercomputing Center

Funder

NSF

Publisher

ACM

Reference40 articles.

1. AnandTech. 2017. Skylake-X's New L3 Cache Architecture. https://www.anandtech.com/show/11464/intel-announces-skylakex-\bringing-18core-hcc-silicon-to-consumers-for-1999/3. (2017). Accessed: 2018-04-03. AnandTech. 2017. Skylake-X's New L3 Cache Architecture. https://www.anandtech.com/show/11464/intel-announces-skylakex-\bringing-18core-hcc-silicon-to-consumers-for-1999/3. (2017). Accessed: 2018-04-03.

2. Arm. 2012. Cortex-A9 Technical Reference Manual. http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388i/DDI0388I_cortex_a9_r4p1_trm.pdf. (2012). Accessed: 2017-04-30. Arm. 2012. Cortex-A9 Technical Reference Manual. http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388i/DDI0388I_cortex_a9_r4p1_trm.pdf. (2012). Accessed: 2017-04-30.

3. An effective on-chip preloading scheme to reduce data access penalty

4. A study of replacement algorithms for a virtual-storage computer

5. Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches

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