Area minimization algorithm for parallel prefix adders under bitwise delay constraints
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ACM Press
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
2. Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis;ACM Transactions on Design Automation of Electronic Systems;2023-03-06
3. EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper);2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17
4. A novel generic modulo‐2 graph with full set taxonomical conversion to parallel prefix adders;International Journal of Circuit Theory and Applications;2022-01-03
5. Structured Digital Design;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
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