Understanding Latency Variation in Modern DRAM Chips-Reference-Cited by-同舟云学术

Understanding Latency Variation in Modern DRAM Chips

Published:2016-06-14 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science
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Author:

Chang Kevin K.¹,Kashyap Abhijith¹,Hassan Hasan²,Ghose Saugata¹,Hsieh Kevin³,Lee Donghyuk¹,Li Tianshi⁴,Pekhimenko Gennady¹,Khan Samira⁵,Mutlu Onur⁶

Affiliation:

1. Carnegie Mellon University, Pittsburgh, PA, USA

2. Carnegie Mellon University & TOBB ETU, Ankara, Turkey

3. Carnegie Mellon University, Pittsburgh, USA

4. Peking University & Carnegie Mellon University, Pittsburgh, PA, USA

5. University of Virginia, Charlottesville, VA, USA

6. ETH Zurich & Carnegie Mellon University, Pittsburgh, PA, USA

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2896377.2901453

Reference83 articles.

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2. H. Bauer etal "Memory: Are Challenges ahead?" March 2016. Available: http://www.mckinsey.com/industries/semiconductors/our-insights/memory-are-challenges-ahead H. Bauer et al. "Memory: Are Challenges ahead?" March 2016. Available: http://www.mckinsey.com/industries/semiconductors/our-insights/memory-are-challenges-ahead

3. Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

4. B. H. Bloom "Space/Time Tradeoffs in Hash Coding with Allowable Errors " CACM July 1970. 10.1145/362686.362692 B. H. Bloom "Space/Time Tradeoffs in Hash Coding with Allowable Errors " CACM July 1970. 10.1145/362686.362692

5. K. Chakraborty and P. Mazumder Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories.\hskip 1em plus 0.5em minus 0.4em\relax Prentice Hall 2002. K. Chakraborty and P. Mazumder Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories.\hskip 1em plus 0.5em minus 0.4em\relax Prentice Hall 2002.

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