BufFormer

Author:

Liang Rongjian1,Nath Siddhartha1,Rajaram Anand1,Hu Jiang2,Ren Haoxing1

Affiliation:

1. NVIDIA

2. Texas A&M University

Publisher

ACM

Reference27 articles.

1. A. Agiza and S. Reda . 2020. Openphysyn: An open-source physical synthesis optimization toolkit . In Proc. WOSET. A. Agiza and S. Reda. 2020. Openphysyn: An open-source physical synthesis optimization toolkit. In Proc. WOSET.

2. FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design;Chu C.;TCAD,2007

3. J. Cong and X. Yuan . 2000. Routing tree construction under fixed buffer locations . In Proc. DAC. 379--384 . J. Cong and X. Yuan. 2000. Routing tree construction under fixed buffer locations. In Proc. DAC. 379--384.

4. D. Dueck. 2009. Affinity propagation: clustering data by passing messages. Citeseer. D. Dueck. 2009. Affinity propagation: clustering data by passing messages. Citeseer.

5. Ward’s Hierarchical Agglomerative Clustering Method: Which Algorithms Implement Ward’s Criterion?

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL;Integration;2024-09

2. ML-based EDA from Research to Production;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

3. An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

4. A Systematic Analysis of Data Diversity in Machine Learning for EDA;Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering;2023-11-03

5. Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

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