Automatic inference of memory fences

Author:

Kuperstein Michael1,Vechev Martin2,Yahav Eran1

Affiliation:

1. Technion

2. ETH Zürich

Abstract

We addresses the problem of automatic verification and fence inference in concurrent programs running under relaxed memory models. Modern architectures implement relaxed memory models in which memory operations may be reordered and executed non-atomically. Instructions called memory fences are provided to the programmer, allowing control of this behavior. To ensure correctness of many algorithms, the programmer is often required to explicitly insert memory fences into her program. However, she must use as few fences as possible, or the benefits of the relaxed architecture may be lost. It is our goal to help automate the fence insertion process. We present an algorithm for automatic inference of memory fences in concurrent programs, relieving the programmer from this complex task. Given a finite-state program, a safety specification and a description of the memory model our algorithm computes a set of ordering constraints that guarantee the correctness of the program under the memory model. The computed constraints are maximally permissive: removing any constraint from the solution would permit an execution violating the specification. These constraints are then realized as additional fences in the input program. We implemented our approach in a pair of tools called fender and blender and used them to infer correct and efficient placements of fences for several non-trivial algorithms, including practical mutual exclusion primitives and concurrent data structures.

Publisher

Association for Computing Machinery (ACM)

Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. AtoMig: Automatically Migrating Millions Lines of Code from TSO to WMM;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2023-01-27

2. Mixed-proxy extensions for the NVIDIA PTX memory consistency model;Proceedings of the 49th Annual International Symposium on Computer Architecture;2022-06-11

3. Fence Synthesis Under the C11 Memory Model;Automated Technology for Verification and Analysis;2022

4. VSync: push-button verification and optimization for synchronization primitives on weak memory models;Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems;2021-04-17

5. Automatic Synthesis of Data-Flow Analyzers;Static Analysis;2021

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