Polylogarithmic concurrent data structures from monotone circuits

Abstract

This article presents constructions of useful concurrent data structures, including max registers and counters, with step complexity that is sublinear in the number of processes, n . This result avoids a well-known lower bound by having step complexity that is polylogarithmic in the number of values the object can take or the number of operations applied to it. The key step in these implementations is a method for constructing a max register , a linearizable, wait-free concurrent data structure that supports a write operation and a read operation that returns the largest value previously written. For fixed m , an m -valued max register is constructed from one-bit multi-writer multi-reader registers at a cost of at most ⌈log m ⌉ atomic register operations per write or read. An unbounded max register is constructed with cost O (min(log v , n )) to read or write a value v . Max registers are used to transform any monotone circuit into a wait-free concurrent data structure that provides write operations setting the inputs to the circuit and a read operation that returns the value of the circuit on the largest input values previously supplied. One application is a simple, linearizable, wait-free counter with a cost of O (min(log n log v , n )) to perform an increment and O (min(log v , n )) to perform a read, where v is the current value of the counter. For polynomially-many increments, this becomes O (log 2 n ), an exponential improvement on the best previously known upper bounds of O ( n ) for exact counting and O ( n 4/5+ϵ ) for approximate counting. Finally, it is shown that the upper bounds are almost optimal. It is shown that for deterministic implementations, even if they are only required to satisfy solo-termination, min(⌈log m ⌉, n -1) is a lower bound on the worst-case complexity for an m -valued bounded max register, which is exactly equal to the upper bound for m ≤ 2 n -1 , and min( n -1, ⌈ log m ⌉ - log(⌈ log m ⌉ + k )) is a lower bound for the read operation of an m -valued k -additive-accurate counter, which is a bounded counter in which a read operation is allowed to return a value within an additive error of ± k of the number of increment operations linearized before it. Furthermore, even in a solo-terminating randomized implementation of an n -valued max register with an oblivious adversary and global coins, there exist simple schedules in which, with high probability, the worst-case step complexity of a read operation is Ω(log n /log log n ) if the write operations have polylogarithmic step complexity.