Technology Mapping into General Programmable Cells-Reference-Cited by-同舟云学术

Technology Mapping into General Programmable Cells

Published:2015-02-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
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Author:

Mishchenko Alan¹,Brayton Robert¹,Feng Wenyi²,Greene Jonathan²

Affiliation:

1. University of California Berkeley, Berkeley, CA, USA

2. Microsemi Corporation, San Jose, CA, USA

Funder

SRC

NSA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2684746.2689082

Reference20 articles.

1. Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. http://www-cad.eecs.berkeley.edu/~alanmi/abc Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. http://www-cad.eecs.berkeley.edu/~alanmi/abc

2. J. Cong and Y. Hwang "Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping " IEEE TCAD'01 Vol. 20(9) pp. 1077--1090. 10.1109/43.945303 J. Cong and Y. Hwang "Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping " IEEE TCAD'01 Vol. 20(9) pp. 1077--1090. 10.1109/43.945303

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