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Author:
Affiliation:
1. Parallel Architectures Group, Universitat Politècnica, de València
2. Departamento de Ingeniería y, Tecnología de Computadores, Universidad de Murcia
3. Department of Computer Engineering, Universitat Politècnica de València
Funder
Fundación Séneca
Ministerio de Economía y Competitividad
European Commission
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2925426.2926280
Reference52 articles.
1. Advanced Micro Devices. http://www.amd.com. {Online; accessed Jan-2016}. Advanced Micro Devices. http://www.amd.com. {Online; accessed Jan-2016}.
2. ARM holdings plc. http://www.arm.com. {Online; accessed Jan-2016}. ARM holdings plc. http://www.arm.com. {Online; accessed Jan-2016}.
3. Intel Corporation. http://www.intel.com. {Online; accessed Jan-2016}. Intel Corporation. http://www.intel.com. {Online; accessed Jan-2016}.
4. N. Agarwal T. Krishna L.-S. Peh and N. K. Jha. GARNET: A detailed on-chip network model inside a full-system simulator. In IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS) pages 33--42 Apr. 2009. N. Agarwal T. Krishna L.-S. Peh and N. K. Jha. GARNET: A detailed on-chip network model inside a full-system simulator. In IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS) pages 33--42 Apr. 2009.
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