Verified compilation on a verified processor-Reference-Cited by-同舟云学术

Verified compilation on a verified processor

Published:2019-06-08 Issue: Volume: Page:
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Container-title:Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation
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Author:

Lööw Andreas¹,Kumar Ramana²,Tan Yong Kiam³,Myreen Magnus O.¹,Norrish Michael⁴,Abrahamsson Oskar¹,Fox Anthony⁵

Affiliation:

1. Chalmers University of Technology, Sweden

2. DeepMind, UK

3. Carnegie Mellon University, USA

4. Data61 at CSIRO, Australia / Australian National University, Australia

5. ARM, UK

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3314221.3314622

Reference5 articles.

1. 2018. IEEE Standard for System Verilog-Unified Hardware Design Specification and Verification Language. IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012) (2018). 2018. IEEE Standard for System Verilog-Unified Hardware Design Specification and Verification Language. IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012) (2018).

2. Eyad Alkassar Mark A. Hillebrand Dirk Leinenbach Norbert W. Schirmer and Artem Starostin. 2008. The Verisoft Approach to Systems Verification. In Verified Software: Theories Tools Experiments (VSTTE). Eyad Alkassar Mark A. Hillebrand Dirk Leinenbach Norbert W. Schirmer and Artem Starostin. 2008. The Verisoft Approach to Systems Verification. In Verified Software: Theories Tools Experiments (VSTTE) .

3. Position paper: the science of deep specification;Appel Andrew W.;Philosophical Transactions of the Royal Society of London A: Mathematical, Physical and Engineering Sciences,2017

4. Putting it all together - Formal verification of the VAMP;Beyer Sven;International Journal on Software Tools for Technology Transfer (STTT),2006

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