Communication-aware Partitioning for Energy Optimization of Large FPGA Designs-Reference-Cited by-同舟云学术

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Communication-aware Partitioning for Energy Optimization of Large FPGA Designs

Published:2017-05-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the on Great Lakes Symposium on VLSI 2017
language:
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Author:

Herath Kalindu¹,Prakash Alok¹,Guiyuan Jiang¹,Srikanthan Thambipillai¹

Affiliation:

1. Nanyang Technological University, Singapore, Singapore

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3060403.3060441

Reference17 articles.

1. Altera. https://www.altera.com/. Altera. https://www.altera.com/.

2. Intel#8482; FPGA Development Tools - Quartus Prime. https://goo.gl/3kMRQN. Intel#8482; FPGA Development Tools - Quartus Prime. https://goo.gl/3kMRQN.

3. PowerPlay Power Analyzer Support Resources. https://goo.gl/1fE7NI. PowerPlay Power Analyzer Support Resources. https://goo.gl/1fE7NI.

4. Xilinx. https://www.xilinx.com/. Xilinx. https://www.xilinx.com/.

5. Towards scalable placement for FPGAs

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-12

2. Power-Aware High-Level Synthesis Flow for Mapping FPGA Designs;2019 Moratuwa Engineering Research Conference (MERCon);2019-07

3. Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2018

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