Power model analysis using variable rate clock network in CMOS processor
Author:
Affiliation:
1. Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore
2. Department of ECE, Sri Krishna College of Technology, Coimbatore
3. Department of Electrical and Electronics Engineering, Sri Krishna College of Technology
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2967878.2967915
Reference18 articles.
1. Ying Teng and BarisTaskin 2015 ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design IEEE Transactions on very large scale Integration (VLSI) Systems 23 11 (NOVEMBER 2015) 2519--2530 Ying Teng and BarisTaskin 2015 ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design IEEE Transactions on very large scale Integration (VLSI) Systems 23 11 (NOVEMBER 2015) 2519--2530
2. Pierre-Emmanuel Gaillardon Xifan Tang Gain Kim and Giovanni De Micheli 2015 A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells IEEE Transactions on very large scale Integration (VLSI) Systems 23 10 (OCTOBER 2015) 2187--2197. Pierre-Emmanuel Gaillardon Xifan Tang Gain Kim and Giovanni De Micheli 2015 A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells IEEE Transactions on very large scale Integration (VLSI) Systems 23 10 (OCTOBER 2015) 2187--2197.
3. JosepRius 2015 Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Non uniform Power Consumption and Interblock Decoupling Capacitors IEEE Transactions on very large scale Integration (VLSI) Systems 23 6 (JUNE 2015.) 993--1004. JosepRius 2015 Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Non uniform Power Consumption and Interblock Decoupling Capacitors IEEE Transactions on very large scale Integration (VLSI) Systems 23 6 (JUNE 2015.) 993--1004.
4. Guoyue Jiang Zhaolin Li Fang Wang and Shaojun Wei 2015 A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks IEEE Transactions on very large scale Integration (VLSI) Systems 23 4 (APRIL 2015) 664--677. Guoyue Jiang Zhaolin Li Fang Wang and Shaojun Wei 2015 A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks IEEE Transactions on very large scale Integration (VLSI) Systems 23 4 (APRIL 2015) 664--677.
5. Xuan Wang Xiaowen Wu Zhehui Wang 2015 Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC IEEE Transactions on very large scale Integration (VLSI) Systems VOL. 23 NO. 2 Pages: 266--279 FEBRUARY 2015. Xuan Wang Xiaowen Wu Zhehui Wang 2015 Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC IEEE Transactions on very large scale Integration (VLSI) Systems VOL. 23 NO. 2 Pages: 266--279 FEBRUARY 2015.
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