Improving processor efficiency by statically pipelining instructions
Author:
Affiliation:
1. University of Mary Washington, Fredericksburg, VA, USA
2. Florida State University, Tallahassee, FL, USA
3. Boise State University, Boise, FL, USA
Publisher
ACM
Reference20 articles.
1. T. Austin E. Larson and D. Ernst. SimpleScalar: An Infrastructure for Computer System Modeling. Computer 35(2):59--67 2002. 10.1109/2.982917
2. M. Benitez and J. Davidson. A Portable Global Optimizer and Linker. ACM SIGPLAN Notices 23(7):329--338 1988. 10.1145/960116.54023
3. A. Bright J. Fritts and M. Gschwind. Decoupled fetch-execute engine with static branch prediction support. Technical report IBM Research Report RC23261 IBM Research Division 1999.
4. H. Corporaal and M. Arnold. Using Transport Triggered Architectures for Embedded Processor Design. Integrated Computer-Aided Engineering 5(1):19--38 1998.
5. W. Dally. Micro-optimization of floating-point operations. In Proceedings of the Conference on Architectural Support for Programming Languages and Operating Systems pages 283--289 1989. 10.1145/70082.68208
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