Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems

Author:

Daya Bhavya K.1,Peh Li-Shiuan1,Chandrakasan Anantha P.1

Affiliation:

1. Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA

Publisher

ACM

Reference23 articles.

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2. Oracle's SPARC T5-2;SPARC T

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4. Fixed latency on-chip interconnect for hardware spiking neural network architectures

5. Æthereal Network on Chip:Concepts, Architectures, and Implementations

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