Sources of parallelism in software pipelining loops with conditional branches
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Published:2000-02
Issue:2
Volume:35
Page:36-45
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ISSN:0362-1340
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Container-title:ACM SIGPLAN Notices
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language:en
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Short-container-title:SIGPLAN Not.
Author:
Milicev Dragan1,
Jovanovic Zoran1
Affiliation:
1. University of Belgrade, School of Electrical Engineering, Department of Computer Engineering and Science
Abstract
The subject of this paper is the instruction-level parallelism and the process of software pipelining loops with conditional branches. First, preconditions for treating such loops are introduced, and some effects of existence of conditional instructions and their outcomes that are important for parallelization are analyzed These effects are emphasized and systematized
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Publisher
Association for Computing Machinery (ACM)
Subject
Computer Graphics and Computer-Aided Design,Software