FPGA-accelerated simulation of variable latency memory systems

Author:

Cılasun Hüsrev1ORCID,Macaraeg Chris2ORCID,Peng Ivy Bo3,Sarkar Abhik2ORCID,Gokhale Maya2

Affiliation:

1. University of Minnesota, United States

2. LLNL, United States

3. KTH, Sweden

Funder

U.S. Department of Energy

Publisher

ACM

Reference32 articles.

1. 2020. LiME. https://github.com/LLNL/lime. 2020. LiME. https://github.com/LLNL/lime.

2. 2020. LiME Applications. https://github.com/LLNL/lime-apps. 2020. LiME Applications. https://github.com/LLNL/lime-apps.

3. 2020. NumPy. github.com/numpy/numpy. 2020. NumPy. github.com/numpy/numpy.

4. 2020. Processor Counter Monitor (PCM). github.com/opcm/pcm. 2020. Processor Counter Monitor (PCM). github.com/opcm/pcm.

5. 2022. Compute Express Link. https://www.computeexpresslink.org. 2022. Compute Express Link. https://www.computeexpresslink.org.

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Quantitative Approach for Adopting Disaggregated Memory in HPC Systems;Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis;2023-11-11

2. REMU: Enabling Cost-Effective Checkpointing and Deterministic Replay in FPGA-based Emulation;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06

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