Fine-grain design space exploration for a cartographic SoC multiprocessor

Abstract

Traditionally, in the field of embedded systems low power consumption and low cost have been always regarded as stringent specification constraints. In recent years, high computational power has become a fundamental requirement as well. This has been mainly determined by the introduction of new features, typical of general-purpose systems, e.g. GUI-based interfaces. In this setting, low cost, low power consumption, significant computational power and short time-to-market are conflicting needs that have to be accommodated. The adoption of a simple multiprocessor on a single chip can be deemed a convenient answer, because it is able to deliver a considerable computing power using low-cost and low-power CPU cores. In this paper, we take into account SPP, a cartographic system to be deployed on hand-held devices. We present the overall methodology used for designing the multiprocessor architecture of its hardware platform, and we focus on the activities that have been carried out to get to the more convenient setting for the system, respect to the specification requirements.The adopted design process includes two phases. The former ( coarse-grain exploration ) is aimed at selecting an architecture suitable to properly support the appliance features; the latter ( finegrain exploration ) is aimed at tuning the parameter values with the purpose of obtaining to the best system setting. We show how this tuning phase for the SPP chipset has involved the selection the clock rate and the cache coherence strategy, and the analysis of bus traffic. Moreover, from the discussed study it becomes evident that further improvements in the system performance have to be pursued possibly operating on the software components.