Affiliation:
1. Seoul National University, Seoul
2. Samsung Electronics, Kiheung
Abstract
Time-to-market pressure and the ever-growing design complexity of multiprocessor system-on-chips have demanded an efficient design environment that enables fast exploration of large design space. In this article, we introduce a new design environment, called SoCDAL, for accelerating multiprocessor system-on-chip design through fast design-space exploration targeting real-time multimedia systems. SoCDAL is a set of mostly automated tools covering system specification, hardware/software estimation, application-to-architecture mapping, simulation model generation, and system verification through simulation. For system specification, the process network model has been widely used for system specification because of its modeling capability. However, it is hard to use for real-time systems design, since its behavior cannot be estimated statically. We introduce a new approach which enables analyzing a process network model statically with some restrictions. For the hardware/software estimation, we analyze codes statically. Application-to-architecture mapping process implements a novel algorithm to support an arbitrary number of processors, with performance evaluation by static scheduling considering communication behavior. Mapping results are used to generate simulation models automatically at several transaction levels to be pipelined to a commercial tool. We show the effectiveness of our approaches by some experimental results with multimedia applications such as JPEG, H.263, and H.264 encoders, as well as an H.264 decoder.
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
Reference54 articles.
1. Metropolis: an integrated electronic system design environment
2. Basten T. and Hoogerbrugge J. 2001. Efficient execution of process networks. In Communication Process Architectures A. Chalmers et al. Eds. IOS Press Bristol UK 1--14. Basten T. and Hoogerbrugge J. 2001. Efficient execution of process networks. In Communication Process Architectures A. Chalmers et al. Eds. IOS Press Bristol UK 1--14.
3. Catapult C Synthesis. 2005. C-based design. http://www.mentor.com/products/c-based_design. Catapult C Synthesis. 2005. C-based design. http://www.mentor.com/products/c-based_design.
4. CDFG. 1998. Control data flow graph toolset. http://poppy.snu.ac.kr/CDFG. CDFG. 1998. Control data flow graph toolset. http://poppy.snu.ac.kr/CDFG.
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