WaFFLe

Author:

Chakraborty Shounak1,Själander Magnus1

Affiliation:

1. Department of Computer Science, Norwegian University of Science and Technology (NTNU), Glshaugen, Trondheim, Norway

Abstract

Managing thermal imbalance in contemporary chip multi-processors (CMPs) is crucial in assuring functional correctness of modern mobile as well as server systems. Localized regions with high activity, e.g., register files, ALUs, FPUs, and so on, experience higher temperatures than the average across the chip and are commonly referred to as hotspots. Hotspots affect functional correctness of the underlying circuitry and a noticeable increase in leakage power, which in turn generates heat in a self-reinforced cycle. Techniques that reduce the severity of or completely eliminate hotspots can maintain functional correctness along with improving performance of CMPs. Conventional dynamic thermal management targets the cores to reduce hotspots but often ignores caches, which are known for their high leakage power consumption. This article presents WaFFLe , an approach that targets the leakage power of the last-level cache (LLC) and hotspots occurring at the cores. WaFFLe turns off LLC-ways to reduce leakage power and to generate on-chip thermal buffers. In addition, fine-grained DVFS is applied during long LLC miss induced stalls to reduce core temperature. Our results show that WaFFLe reduces peak and average temperature of a 16-core based homogeneous tiled CMP with up to 8.4 ֯ C and 6.2 ֯ C, respectively, with an average performance degradation of only 2.5 %. We also show that WaFFLe outperforms a state-of-the-art cache-based technique and a greedy DVFS policy.

Funder

Marie Curie

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores;ACM Transactions on Embedded Computing Systems;2024-06-29

2. TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture;2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2024-05-27

3. DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore;IEEE Transactions on Parallel and Distributed Systems;2023-02-01

4. HTree: Hardware Trojan Attack on Cache Resizing Policies;IEEE Embedded Systems Letters;2023

5. STIFF;Proceedings of the 19th ACM International Conference on Computing Frontiers;2022-05-17

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