Design Space Exploration of SABER in 65nm ASIC-Reference-Cited by-同舟云学术

Design Space Exploration of SABER in 65nm ASIC

Published:2021-11-15 Issue: Volume: Page:
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Container-title:Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security
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Author:

Imran Malik¹,Almeida Felipe¹,Raik Jaan¹,Basso Andrea²,Roy Sujoy Sinha³,Pagliarini Samuel¹

Affiliation:

1. Tallinn University of Technology, Tallinn, Estonia

2. University of Birmingham, Birmingham, United Kingdom

3. Graz University of Technology, Graz, Austria

Funder

European Social Fund

Estonian Research Council

European Union's Horizon 2020 research and innovation programme

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3474376.3487278

Reference12 articles.

1. A Lightweight Implementation of Saber Resistant Against Side-Channel Attacks

2. Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols;Banerjee Utsav;IACR Transactions on Cryptographic Hardware and Embedded Systems,2019

3. A Side-Channel-Resistant Implementation of SABER

4. Viet B. Dang Farnoud Farahmand Michal Andrzejczak and Kris Gaj. 2019. Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign. In 2019 International Conference on Field-Programmable Technology (ICFPT). 206--214. Viet B. Dang Farnoud Farahmand Michal Andrzejczak and Kris Gaj. 2019. Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign. In 2019 International Conference on Field-Programmable Technology (ICFPT). 206--214.

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