P4LRU: Towards An LRU Cache Entirely in Programmable Data Plane

Author:

Zhao Yikai1ORCID,Liu Wenrui1ORCID,Dong Fenghao1ORCID,Yang Tong1ORCID,Li Yuanpeng1ORCID,Yang Kaicheng1ORCID,Liu Zirui1ORCID,Jia Zhengyi2ORCID,Yang Yongqiang2ORCID

Affiliation:

1. Peking University, Beijing, China

2. Huawei Cloud Computing Technologies Co Ltd, Beijing, China

Funder

National Key R&D Program of China

National Natural Science Foundation of China (NSFC)

Publisher

ACM

Reference61 articles.

1. All related codes of our three system. https://github.com/P4-LRU/P4-LRU. All related codes of our three system. https://github.com/P4-LRU/P4-LRU.

2. Barefoot tofino and tofino 2 switches. https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch/tofino-2-series.html. Barefoot tofino and tofino 2 switches. https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch/tofino-2-series.html.

3. The caida anonymized internet traces. http://www.caida.org/data/overview/. The caida anonymized internet traces. http://www.caida.org/data/overview/.

4. Data plane development kit. http://doc.dpdk.org/guides-18.02/. Data plane development kit. http://doc.dpdk.org/guides-18.02/.

5. Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

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