Device and Circuit Level Performance Analysis of a New Nanoscale DGJL MOSFET Design Using an Accurate Numerical Computation-Reference-Cited by-同舟云学术

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Device and Circuit Level Performance Analysis of a New Nanoscale DGJL MOSFET Design Using an Accurate Numerical Computation

Published:2018-12-26 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 7th International Conference on Software Engineering and New Technologies
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Author:

Chebaki Elasaad¹,Djeffal Faycal¹,Bentrcia Toufik²,Ferhati Hichem³

Affiliation:

1. Advanced Electronics Laboratory (LEA), Department of Electronics, Batna, Algeria

2. Department of Physics, University of Batna 1, Batna, Algeria

3. Advanced Electronics Laboratory (LEA), Department of Electronics, University of Batna 2, Batna, Algeria

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3330089.3330471

Reference16 articles.

1. Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold

2. Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs

3. Dual-gate operation and volume inversion in n-channel SOI MOSFET's

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