An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs

Author:

Das Sabya1,Aggarwal Rajat1,Wang Zhiyong1

Affiliation:

1. Xilinx Inc, San Jose, CA, USA

Publisher

ACM

Reference17 articles.

1. Ultrascale Architecture Xilinx Inc. http://www. xilinx.com/products/technology/ultrascale.html 2015. [Online; accessed 20-Jan-2016]. Ultrascale Architecture Xilinx Inc. http://www. xilinx.com/products/technology/ultrascale.html 2015. [Online; accessed 20-Jan-2016].

2. Physical synthesis for performance optimization

3. Rumble: An incremental timing-driven physical-synthesis optimization algorithm. Computer-Aided Design of Integrated Circuits and Systems;Papa D.A.;IEEE Transactions on,2008

4. Predicting interconnect delay for physical synthesis in a fpga cad flow. Very Large Scale Integration (VLSI) Systems;Manohararajah V.;IEEE Transactions on,2007

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