Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks

Author:

Tran Thai-Ha1ORCID,Le Anh-Tien1ORCID,Hoang Trong-Thuc1ORCID,Hoang Van-Phuc2ORCID,Pham Cong-Kha1ORCID

Affiliation:

1. University of Electro-Communications, Tokyo, Japan

2. University of Electro-Communications, Hanoi, Japan

Publisher

ACM

Reference20 articles.

1. Chaotic Clock Driven Cryptographic Chip: Towards a DPA Resistant AES Processor;Moursy A. A.;IEEE Trans. on Emerging Topics in Comp.,2020

2. Success rate model for fully AES-128 in correlation power analysis

3. An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA

4. B. Hettwer , K. Das , S. Leger , S. Gehrer , and T. Güneysu . Aug . 2020. Lightweight Side-Channel Protection using Dynamic Clock Randomization . In Proc. of Int. Conf. on Field-Prog. Logic and Appl. (FPL) ( Gothenburg, Sweden). 200--207. B. Hettwer, K. Das, S. Leger, S. Gehrer, and T. Güneysu. Aug. 2020. Lightweight Side-Channel Protection using Dynamic Clock Randomization. In Proc. of Int. Conf. on Field-Prog. Logic and Appl. (FPL) (Gothenburg, Sweden). 200--207.

5. D. Fledel and A. Wool . Aug . 2018. Sliding-Window Correlation Attacks Against Encryption Devices with an Unstable Clock . In Proc. of Selected Areas in Crypto. (SAC) (Calgary, AB, Canada). 193--215 . D. Fledel and A. Wool. Aug. 2018. Sliding-Window Correlation Attacks Against Encryption Devices with an Unstable Clock. In Proc. of Selected Areas in Crypto. (SAC) (Calgary, AB, Canada). 193--215.

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