System-in-Packages with Low Power Loss for Future Voltage Regulators-Reference-Cited by-同舟云学术

System-in-Packages with Low Power Loss for Future Voltage Regulators

Published:2010 Issue:9 Volume:130 Page:1630-1635
ISSN:0385-4221
Container-title:IEEJ Transactions on Electronics, Information and Systems
language:en
Short-container-title:IEEJ Trans.EIS

Author:

Hashimoto Takayuki¹,Kawashima Tetsuya¹,Shiraishi Masaki¹,Akiyama Noboru²,Uno Tomoaki³,Matsuura Nobuyoshi³

Affiliation:

1. Hitachi Research Laboratory, Hitachi Ltd.

2. Hitachi Institute of Technology, Hitachi Ltd.

3. Power Devices Business Unit, Renesas Electronics Corp.

Publisher

Institute of Electrical Engineers of Japan (IEE Japan)

Subject

Electrical and Electronic Engineering

Link

http://www.jstage.jst.go.jp/article/ieejeiss/130/9/130_9_1630/_pdf

Reference10 articles.

1. (1) T. Hashimoto, M. Shiraishi, N. Akiyama, T. Kawashima, T. Uno, and N. Matsuura : “System in Package (SiP) with reduced parasitic inductance for future voltage regulator”, IEEE Trans. Power Electron., Vol. 24, No. 6, pp. 1547-1553 (2009-6)

2. (2) Y. Kawaguchi, T. Kawano, H. Takei, S. Ono, and A. Nakagawa : “Multi chip module with minimum parasitic inductance for new generation voltage regulator”, in Proc. IEEE ISPSD'05, pp. 371-374 (2005-5)

3. (3) T. Hashimoto, T. Uno, Y. Sato, M. Shiraishi, T. Kawashima, and N. Matsuura : “Advanced power SiP with wireless bonding for voltage regulators”, in Proc. IEEE ISPSD'07, pp. 125-128 (2007-5)

4. (4) T. Hashimoto, T. Kawashima, T. Uno, Y. Sato, and N. Matsuura : “System in package with mounted capacitor for reduced parasitic inductance in voltage regulators”, in Proc. IEEE APEC'08, Vol. 1, pp. 187-191 (2008)

5. (5) M. Darwish, C. Yue, K. H. Lui, F. Giles, B. Chan, K. Chen, D. Pattanayak, Q. Chen, K. Terrill, and K. Owyang : “A new power W-gate trench MOSFET (WMOSFET) with high switching performance”, in Proc. IEEE ISPSD'03, pp. 24-27 (2003-4)