Polycrystalline silicon gate originated CMOS device failure investigated by Scanning Spreading Resistance Microscopy

Author:

Doering StefanORCID,Wachowiak Andre,Rochel Markus,Nowak Christian,Hoffmann Marko,Winkler Uwe,Richter Mirco,Roetz Hagen,Eckl Stefan,Mikolajick Thomas

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. Doping of n+ and p+ polysilicon in a dual-gate CMOS process;Wong,1988

2. Anomalous C-V characteristics of implanted poly MOS structure in n+/p+ dual-gate CMOS technology;Lu;IEEE Electron Device Lett.,1989

3. A study on the physical mechanism in the recovery of gate capacitance to Cox in implanted polysilicon MOS structures;Lee;IEEE Electron Device Lett.,1992

4. Separation of d.c. and a.c. competing effect of polysilicon-gate depletion in deep submicron CMOS circuit performance;Lin;Solid State Electron.,1996

5. Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors;Tuinhout,1997

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