“Smart” TDDB algorithm for investigating degradation in high-κ gate dielectric stacks under constant voltage stress-Reference-Cited by-同舟云学术

“Smart” TDDB algorithm for investigating degradation in high-κ gate dielectric stacks under constant voltage stress

Published:2009-03 Issue:3 Volume:86 Page:287-290
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Young Chadwin D.,Bersuker Gennadi,Tun Joey,Choi Rino,Heh Dawei,Lee Byoung Hun

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference16 articles.

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2. Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kimura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimoto, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, N. Nagashima, in: high-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (100) and (110) substrates, Presented at Electron Devices Meeting 2006, IEDM’06 International, 2006.

3. G. Bersuker, N. Chowdhury, C. Young, D. Heh, D. Misra, R. Choi, in: Progressive breakdown characteristics of high-K/metal gate stacks, Presented at International Reliability Physics Symposium, 2007.

4. N.A. Chowdhury, G. Bersuker, C. Young, R. Choi, S. Krishnan, D. Misra, Microelectronic Engineering, 85 (2008) 27–35.

5. Validity of constant voltage stress based reliability assessment of high-/spl kappa/ devices

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