Author:
Jang Wei-Luen,Wang Tai-Siang,Lai Yen-Fen,Lin Kwang-Lung,Lai Yi-Shao
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference23 articles.
1. Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition;Lai;Microelectron Reliab,2006
2. JEDEC solid state technology association, JESD22-B110: Subassembly Mechanical, Shock; 2001.
3. JEDEC solid state technology association, JESD22-B110: board level drop test method of component for handheld electronic products; 2003.
4. Chheda BV, Manian RS, Ghaffarian R. Thermal shock and drop test performance of lead-free assemblies with No-underfill, Corner-underfill and Full-underfill. In: Proceedings - electronic components and technology conference; 2010. p. 935–42.
5. Sun L, Cunningham S, DeReus D, Morris A. Investigation of board-level and package-level drop reliability of RF MEMS package, ASME international mechanical engineering congress and exposition. In: Proceedings 5; 2010. p. 225–30.
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