1. Suk SD, Lee SY, Kim SM, Yoon EJ, Kim MS, Li M, et al. High performance 5nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability. In: Tech dig of int’l electron device meet; 2005. p. 717–20.
2. Bidal G, Boeuf F, Denorme S, Loubet N, Huguenin JL, Perreau P, et al. High velocity Si-nanodot: a candidate for SRAM applications at 16nm node and below. In: Tech dig symp of VLSI tech; 2009. p. 240–1.
3. Chen J, Saraya T, Miyaji K, Shimizu K, Hiramoto T. Experimental study of mobility in [110]- and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI. In: Tech dig symp of VLSI tech; 2008. p. 32–3.
4. Chen J, Saraya T, Hiramoto T. High hole mobility in multiple silicon nanowire gate-all-around pMOSFETs on (110) SOI. In: Tech dig symp of VLSI tech; 2009. p. 90–1.
5. Measurement of carrier mobility in silicon nanowires;Gunawan;Nano Lett,2008