8T vs. 6T SRAM cell radiation robustness: A comparative analysis

Author:

Alorda Bartomeu,Torrens Gabriel,Bota Sebastià,Segura Jaume

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference24 articles.

1. International technology roadmap for semiconductors. [July 2010].

2. An SRAM design in 65-nm technology node featuring read and write–assist circuits to expand operating voltage;Pilo;IEEE J Solid-State Circuits,2007

3. SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction;Zhang;IEEE J Solid-State Circuits,2007

4. A 45-nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues;Akamatsu;IEEE J Solid-State Circuits,2008

5. A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode;Kim;IEEE J Solid-State Circuits,2009

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