Determination of the stress level for voltage screen of integrated circuits-Reference-Cited by-同舟云学术

Determination of the stress level for voltage screen of integrated circuits

Published:2010-09 Issue:9-11 Volume:50 Page:1210-1214
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Kho R.M.,Moonen A.J.,Girault V.M.,Bisschop J.,Olthof E.H.T.,Nath S.,Liang Z.N.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference10 articles.

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2. Aitken RC. Test generation and fault modeling for stress testing. In: Proceedings of the international symposium on quality electronic design, ISQED; 2002. p. 95–9.

3. Khalil MA, Wey CL. Extreme voltage stress vector generation of analog CMOS ICs for gate oxide reliability enhancement. In: ITC international test conference; 2001. p. 348–57.

4. Bosworth J, Reinhart A. Sector guide for implementing high voltage stress test. Motorola, 68MWS00088B; 2001.

5. Technique for determining a prudent voltage stress to improve product quality and reliability;Blish;Microelectron Reliab,2000

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