Failure signature analysis of power-opens in DDR3 SDRAMs

Author:

Li Tan,Lee HosungORCID,Bak Geunyong,Baeg Sanghyeon

Funder

MOTIE

KSRC

Ministry of Science, ICT & Future Planning

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference8 articles.

1. Opens localization on silicon level in a Chip Scale Package using space domain reflectometry;Gaudestad;Microelectron. Reliab.,2013

2. Redundant C4 power pin placement to ensure robust power grid delivery;Logan,2013

3. The effects of defects on high-speed boards;Parker,2005

4. A $di/dt$ compensation technique in delay testing by disconnecting power pins;Baeg;IEEE Trans. Instrum. Meas.,2009

5. DDR3 SDRAM Standard;JEDEC,2012

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