The stress analysis and parametric studies for the low-k layers of a chip in the flip-chip process-Reference-Cited by-同舟云学术

The stress analysis and parametric studies for the low-k layers of a chip in the flip-chip process

Published:2016-10 Issue: Volume:65 Page:198-204
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Lin Lin,Wang Jun,Wang Lei,Zhang Wenqi

Funder

National Science and Technology Major Project of China

National Nature Science Foundation of China

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference19 articles.

1. 14nm chip package interaction development with Cu pillar bump flip chip package;Kuo,2015

2. Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste;Cho,2015

3. Chip-package interaction: challenges and solutions to mechanical stability of back end of line at 28nm node and beyond for advanced flip chip application;Kuechenmeister,2012

4. Design for reliability with a new modeling methodology for chip to package interaction;Rao,2015

5. Chip-package interaction in 3D stacked IC packages using finite element modelling;Vandevelde;Microelectron. Reliab.,2014

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