Author:
Melamed Samson,Watanabe Naoya,Nemoto Shunsuke,Shimamoto Haruo,Kikuchi Katsuya,Aoyagi Masahiro
Funder
Japan Society for the Promotion of Science
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference18 articles.
1. Power-constrained CMOS scaling limits;Frank;IBM J. Res. Dev.,2002
2. Junction-level thermal analysis of 3-D integrated circuits using high definition power blurring;Melamed;IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.,2012
3. Thermal analysis of hot spots in advanced 3D-stacked structures;Torregiani,2009
4. Thermal performance of 3D ICs: analysis and alternatives;Santos,2014
5. A novel method of hotspot temperature reduction for a 3D stacked CMOS IC chip device fabricated on an ultrathin substrate;Kato;J. Micromech. Microeng.,2013
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