Experimental study of carrier transport in multi-layered structures-Reference-Cited by-同舟云学术

Experimental study of carrier transport in multi-layered structures

Published:2007-04 Issue:4-5 Volume:47 Page:610-614
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Tao Guoqiao,Ouvrard Cedric,Chauveau Helene,Nath Som

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference8 articles.

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2. Kim K. Future outlook of NAND Flash technology for 40nm node and beyond. In: NVSMW, 2006. p. 9–11.

3. van Schaijk R, et al. A novel SONOS memory with HfSiON/Si3N4/HfSiON stack for improved retention. In: NVSMW, 2006. p. 50–1.

4. Inumiya S, et al. A thermally-stable sub-0.9nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrication of hp45 LOP devices. In: IEDM technical digest 2005, p. 23–6.

5. Evseev S. Kinetics of conduction–related voltage instabilities in thick nitride/oxide dielectrics. In: WODIM, 2006.

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