Efficient statistical capacitance extraction of nanometer interconnects considering the on-chip line edge roughness-Reference-Cited by-同舟云学术

Efficient statistical capacitance extraction of nanometer interconnects considering the on-chip line edge roughness

Published:2012-04 Issue:4 Volume:52 Page:704-710
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Yu Wenjian,Zhang Qingqing,Ye Zuochang,Luo Zuying

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference17 articles.

1. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness;Asenov;IEEE Trans Electron Dev,2003

2. Impact of line-edge roughness on resistance and capacitance of scaled interconnects;Stucchi;Microelectron Eng,2007

3. Twaddle FJ, et al. RC variability of short-range interconnects. In: Proceedings IWCE; 2009. p. 1–4.

4. Bi Y, et al. Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. In: Proceedings ASP-DAC; 2011. p. 61–6.

5. Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness;Poliakov;Microelectron Reliab,2011

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