1. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors;Ghani,2003
2. High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL;Lee,2005
3. A 45nm logic technology with high-K+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging;Mistry,2007
4. Silicon CMOS devices beyond scaling;Haensch;IBM J. Res. Dev.,2006
5. Totally relaxed GexSi1−x layers with low threading dislocation densities grown on Si substrate;Fitzgerald;Appl. Phys. Lett.,1991