1. Process technology scaling in an increasingly interconnect dominated world;Clarke,2014
2. Challenges in low-k integration of advanced Cu BEOL beyond 14 nm node;Inoue,2013
3. Improvement of RC performance for advanced ULK/Cu interconnects with CVD hybrid dielectric/metal liner;Tagami,2011
4. RC performance evaluation of interconnect architecture options beyond the 10-nm logic node;Kincal;IEEE Trans Electron Devices,2014
5. An enhanced 16 nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications;Wu,2014